The invention relates to a data processing system and a method for controlling the latter with the data processing system having a central processing unit (CPU), a main memory and a system bus which can be connected to the main memory and other functional units. The invention also relates to a CPU board for a data processing system in which the CPU is mounted on its own board.
Normally, the CPU, main memory and the input/output units (I/O units) or their controllers are each on a board, also referred to as a card. All functional units connected to the system bus are thus controlled centrally by the central processing unit (CPU), e.g. by a microprocessor. As a result, communication between the functional units and the CPU always takes place via the system bus.
For example, if an I/O unit wishes to transfer data with the main memory, i.e., input data to the main memory or output data from the main memory, the I/O unit sends a signal to the system bus; on the basis of this signal, the CPU is "halted" for a brief period of time while the I/O unit is permitted to directly access the main memory, a process also referred to as DMA (direct memory access).
Since a great many direct accesses are made to the main memory, particularly during peak load operation, jams and long waiting periods occur; this is due to the fact that the system bus timing is standardized and therefore cannot be accelerated to any speed, especially since all plug-in cards on the system bus must adhere to certain invariable timings.
An entire range of techniques are known for the simultaneous processing of as many tasks as possible in data processing systems. For example, so-called cache memories are used as small, fast buffers and are placed on the same board as the CPU. The CPU then outputs the data from the main memory via the system bus and writes these data to the fast cache memory located on the CPU board. If the CPU attempts to reaccess this data, it no longer has to transfer the data from the main memory via the relatively slow system bus, but can directly access the fast cache memory.
Due to advanced integration technology, it has become possible to place the CPU and main memory on a single board. Since communication between the I/O units and the main memory continues to take place via the system bus, the latter is blocked to the main memory by frequent DMA accesses, i.e. accesses by I/O units with direct access, so that long waiting periods again occur.